1. Field of the Invention
This invention relates to a method and apparatus for increasing the operational efficiency of flash memory devices and electronic units that use flash memory devices.
2. Background
Solid-state drives (SSDs) have become increasingly commonplace in many electronic units over the past number of years. The majority of these SSDs use flash memory devices in order to store data.
Flash memory devices typically comprise floating-gate field effect transistors (FETs) as their storage element which may implement NOR flash memory and/or NAND flash memory. A floating-gate FET comprises a second, floating gate in addition to the normal gate found in the FET. By setting the electronic charge on the floating gate of the FET, the threshold voltage (VT) of the FET can be altered to reflect a binary ‘1’ or a binary ‘0’ in a single level flash cell, or, more complex binary values in multi-level flash cells (MLCs).
The flash memory devices are arranged in blocks, with each block comprising a plurality of pages, and each page comprising a plurality of bytes. Usually, a page comprises 512, 2048 or 4096 bytes. In some case, the page may comprise an even greater more of bytes.
An electrical stimulus, which is set with regard to operating parameters of the flash memory device, is applied to the flash memory device to set the binary value in the flash memory device.
The operating parameters of a flash memory device may comprise one or more of a read voltage level, a write voltage level, an erase voltage level, a read current level, a write current level, an erase current level, a read voltage duration, a write voltage duration, an erase voltage duration, a threshold current, a threshold voltage, a rate of increase of current and voltages, a number of repeated cycles of application of current and voltages for a single program operation or erase operation, a rate of change of currents and voltages during the repeated cycles, a size of steps taken during repeat cycles and/or a pass voltage.
Voltages used in flash memory devices vary in the range of almost 0V to 35V. Current used in flash memory devices vary in the range of a few micro amps to less then 100 milliamps. The number of repeat cycles typically varies from 1 cycle to 20 cycles.
Each of the operating parameters are instantiated by control registers values, or part of a control register value. The control register is a physical piece of memory typically containing eight bits, which encode the operating parameters.
Therefore, throughout the following specification, any reference to operating parameters should be understood to refer to the value stored in the control register. References to the electrical stimulus shall be understood to refer to the actual electrical signals applied to the flash memory device.
A flash memory drive or flash memory unit may contain one or more flash memory devices.
One of the problems with flash memory devices is that the floating-gate FETs degrade over time with every program operation, such as a read operation or a write operation, and, also with every erase operation which is carried out on the flash memory device. After each operation, the structure of the storage element in the floating-gate FETs can become eroded making the floating-gate FET less efficient at changing state between a binary ‘1’ and a binary ‘0’.
The amount of degradation caused to the floating-gate FET on each occasion is proportional to the current levels, voltage levels and the exposure times of the current and voltage levels on the floating-gate FET. The electrical stimulus on the floating-gate FET, the number of repetitions of the electrical stimulus on the floating-gate FET and the rate of change of the electrical stimulus on the floating-gate FET are all factors which are used to perform write and/or erase operations on the floating-gate FETs used in the flash memory device, and consequently are all factors in the degradation levels of the floating gate FETs.
Another problem which currently affects the flash memory devices is that an electrical charge, in the form of implanted electrons, remains in an insulating oxide portion of the floating-gate FET of the flash memory device. This electrical charge obstructs the flow of electrons on and off the insulating oxide portion the floating-gate FET, thus making the floating-gate FET progressively more reluctant to change state between binary ‘1’ and binary ‘0’. This electrical charge increases such a time as the flash memory device cannot be programmed or erased reliably.
Yet a further problem with the flash memory devices is leakage of electrical charge from the floating gate of the floating-gate FET over time. It is important to ensure that enough charge is placed on the floating gate, such that the floating-gate FET will remain set in the same logic state for a prescribed period of time, known as a retention period. This retention period is typically between 3 months to 10 years depending on the intended application of the flash memory device. Over time, electrical charge placed on the floating gate will leak off the electrically isolated gate and the rate at which the charge leaks off the floating gate will, in part, determine the operational lifetime of the flash memory device.
The above mentioned problems reduced the operational efficiency of flash memory devices and a solution has been long since sought to overcome these problems. The flash memory devices have a finite operational lifetime as a result of these problems, and typically, this operational lifetime is up to 100,000 program and/or erase operations for single level cells, or up to 10,000 program and/or erase operations for MLCs.
Thus, the amount of electrical stimulus, and oxide degradation which is associated with that electrical stimulus, that is used to place and extract quantities of electrons onto and from the floating gate of the flash memory device has to be balanced against the ability of the flash memory device to retain those electrons for the above-mentioned retention period in order to provide a flash memory device which is as operationally efficient as possible.
If particularly high operating parameters are used for a long period of time, implantation occurs relatively quickly and thus the degradation of the flash memory device will occur relatively quickly in comparison to flash memory devices that use operating parameters having lower electrical stimulus levels.
Alternatively, if low currents or voltages are set as the operating parameters, then the flash memory will quickly become unusable as even the smallest amount of degradation to the flash cells will make it very difficult for the flash memory to be correctly written to or read from using the low current or voltage signals. Furthermore, low levels of charge on the floating gate may cause the data retention to be relatively short as the charge leaks from the insulated floating gate over time. If a low level of charge is used on the floating gate, the data retention will be relatively short and the operational lifetime of the flash memory device will be significantly reduced.
The role of a design engineer in choosing the operational parameters for a flash memory device is therefore very important if a good balance is to be achieved. However, at present the setting of the operating parameters for the flash memory devices is not a highly scientific process. Typically, the design engineer will use a set of operating parameters that have been found to be appropriate in previous batches of flash memory devices that have been manufactured. As the design engineer is not a way of how the flash memory devices will be deployed, a ‘middle of the road’ approach is taken when choosing the operating parameters. Clearly, in certain situations depending on the operations performed by the flash memory devices, this may not be the correct approach.
Due to manufacturing process variations, material variations and the like, a generic set of operating parameters will not be ideally suited to all batches of flash memory devices. In other words a generic operating parameter set will not be ideally suited to any particular batch of flash memory devices in order to fully exploit that particular batch of flash memory devices. Each batch of flash memory devices will have a potential for longevity which is based on that batch's intrinsic endurance and retention characteristics.
Basing the choice of the operating parameters on historical data from previously manufactured batches of flash memory devices is not wholly reliable and can lead to accelerated degradation of the flash memory devices and consequently a shorter operational lifetime for that flash memory device.
Furthermore, as the operating parameters are set at the time of manufacture of the flash memory devices, the operating parameters are unlikely to be ideally suited to each flash memory device during all of the stages of the flash memory device's operational lifetime. This is due to the implantation and degradation progresses which alter the behaviour of the flash memory devise and resultantly some or all of the operating parameters are no longer ideal.
The rate of degradation of a flash memory device is heavily dependent on the type of application that the flash memory device experiences. For example, a flash memory device used within a memory stick can expect to encounter less state changes, and so does not require a large endurance level, but will experience a relatively large number of periods of power down, and thus require good retention times. On the contrary, a flash memory device used within an enterprise storage array will experience substantially the opposite—frequent state changes but few power down periods.
At present, it is known to use wear-levelling techniques so that the flash memory devices in the flash memory drives are evenly degraded over time. A software routine in the electronic unit which comprises the flash memory devices, or, the flash memory drive itself keeps track of which flash memory devices have been used and manages the reading and writing of data to and from the flash memory devices so that all of the flash memory devices are read from and written to in substantially equal amounts when compared with one another. In this manner, the overall operating lifetime of the flash memory device can be increased as the effects of the degradation of the read/write operations are spread across all of the flash cells in the flash memory device.
Whilst this solution is advantageous, there are still problems since this arrangement does not attempt to stem the wear-out and degradation of the flash memory devices, but rather tries to deploy the wear-out and degradation evenly. The controllers make no attempt to modify operating parameters via the control registers over the operational lifetime of the flash memory device nor do the controllers attempt to compensate for the different operating functions which the flash memory devices will experience.
It is also known for a flash memory device to allow the electrical stimulus levels to be changed over the lifetime of a floating-gate FET; however, the operating parameters are not altered. That is to say, a floating-gate FET may have an operating parameter for a maximum number of repeat cycles for writing to a flash memory device. If the flash memory device has not been successfully written to within that maximum number of repeat cycles, then the flash memory device may be flagged as inoperable and a different flash memory device on the flash memory drive is selected to be written to. At the beginning of the lifetime of a floating-gate FET, although the maximum repeat cycle value stored in the control register may be 15, only 5 attempts may be carried out. As the floating-gate FET becomes older, the number of attempts that are carried out increase up to the maximum number as defined by the operating parameter in the control register. In this manner, it is clear that the electrical stimulus may be increased as a flash memory device becomes older, however, the operating parameters do not change. Thus, while the electrical stimulus between subsequent programming and/or erasing operations may be altered, the registers values never change. The operating parameters are calculated at the flash memory device manufacturing plant, instantiated at the flash memory device manufacturing plant and do not change over the lifetime of the flash memory devices. Heretofore, the operating parameters have been considered as sacrosanct and fixed subsequent to the initial setting of the parameters at the time of manufacture. The variance in the electrical stimulus applied to the floating-gate FET is always limited to upper and/or lower thresholds set by the operating parameters of the floating-gate FET.
The flash memory devices will ultimately degrade due to the coarse nature of the read/write operations that are performed upon them.
It is a goal of the present invention to provide an apparatus/method that overcomes at least one of the above mentioned problems, and increases the operating lifetime of a flash memory device, thus increasing the operational lifetime of an electrical unit comprising the flash memory devices.